1. Field of the Invention
This invention relates to a unique word detecting apparatus and method for detecting a unique word in digital communication using a time division multiple access method (hereinafter called the "TDMA method") for a cordless telephone, that is, a personal handy-phone system (PHS), which is still simpler than a mobile-phone which has been gaining popularity in recent years.
The PHS standard is specified as "STD-28" standard by the Research and Development Center for Radio System (RCR), which is an affiliated agency of the Ministry of Posts and Telecommunications in Japan.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a configuration example of a conventional unique word detecting apparatus for detecting a unique word specified in "STD-28" of the above-mentioned RCR.
In FIG. 1, reference numeral 1 shows a 32-bit shift register, in which 32 pieces of cascade-connected D-latch indicated by reference numeral 1-0 through 1-31 are arranged. To the 32-bit shift register 1, a clock CLK and an external data ED are externally inputted, the clock CLK is inputted to each of D latches 1-0 through 1-31, and the external data ED is inputted in:to the D latch 1-0. Consequently, because 32 pieces of D latch 1-0 through 1-31 input and hold the external data ED bit by bit in synchronism with the clock CLK, a total of 32 bits of data are held in the 32-bit shift register 1.
Reference numeral 2, and 3-0 through 3-31 all indicate coincidence detecting circuits.
The coincidence detecting circuit 2 stores a 32-bit unique word UW specified in the "STD-28" standard of the above RCR and compares the 32-bit data held by the 32-bit shift register 1 with it bit by bit, and outputs a coincidence detecting signal CD when all 32 bits coincide.
32 pieces of coincidence detecting circuits 3-0 through 3-31 stores a unique word for comparison (hereinafter called the "comparison word") with an error in 1 bit, which differs from the original 32-bit unique word UW, respectively, and compares the comparison words UW-0 through UW-31 with the data held by the 32-bit shift register 1 bit by bit, and outputs the coincidence detecting signal CD when all the 32 bits coincide.
An internal construction of each coincidence detecting circuit 2, 3-0 through 3-31 is, in principle, common.
That is, in each of the coincidence detecting circuits 2, 3-0 through 3-31, a memory circuit indicated by reference numeral 4, and 5-0 through 5-31 is installed, respectively, and in addition, an XNOR gate indicated by reference numeral 100 through 131 and an AND gate indicated by reference numeral 132 are installed, respectively.
The memory circuit 4 installed to the coincidence detecting circuit 2 stores the original 32-bit unique word UW The memory circuits 5-0 through 5-31 installed to the coincidence detecting circuits 3-0 through 3-31, respectively, store 32-bit comparison words UW-0 through UW-31 with an error in 1 bit, respectively (in the case of the example shown in FIG. 1, the comparison word UW-0 with an error in the 0th bit is stored in the memory circuit 5-0 installed to the coincidence detecting circuit 3-0 and the comparison word UW-31 with an error in the 31st bit is stored in the memory circuit 5-31 installed to the coincidence detecting circuit 3-31).
The XNOR gates 100 through 131 of each of the coincidence detecting circuits 2, 3-0 through 3-31 detect, respectively, whether the 0th-bit through 31st bit of the data stored in the D latches 1-0 through 1-31 of the 32-bit shift register 1 coincide with the 0th bit through the 31st bit of the unique word UW or comparison word UW-0 through UW-31. The AND gate 132 of each coincidence detecting circuits 2, 3-0 through 3-31 outputs the coincidence detecting signal CD when all the XNOR gates 100 through 131 detect coincidence. With this operation, in each of the coincidence detecting circuits 2, 3-0 through 3-31, whether the unique word UW and comparison words UW-0 through UW-31 coincide with the 32-bit data stored in the 32-bit shift register 1 is detected.
In addition, reference numeral 6 indicates an OR gate to which the coincidence detecting signals CD of all the coincidence detecting circuits 2, 3-0 through 3-31 are inputted. Reference numeral 7 indicates a D latch to which the output signals of the OR gate 6 and clock CLK are inputted and which latches the output of the OR gate 6 at the falling edge of the clock CLK. Consequently, when a coincidence detecting signal CD is outputted from at least either one of the coincidence detecting circuits 2, 3-0 through 3-31, the OR gate 6 outputs the detecting signal indicating that the unique word has been detected and the D latch 7 latches the output of the OR gate 6 at the falling edge of the clock CLK.
Now, description is made on the operation of a conventional unique word detecting apparatus with the above-mentioned configuration.
First of all, the 32-bit shift register 1 inputs the external data (TDMA frame data), as shown in FIG. 2, bit by bit in synchronism with the external clock CLK and latches the 32-bit data as a whole.
The TDMA frame data shown in FIG. 2 is specified by the "STD-28" standard of RCR as mentioned above and consists of ramp time (R) for transient response, start symbol (SS), preamble code (PR) which is a repetition of "1001," unique word (UW), and finally original communication data (I) in that order.
By the way, when the Latest external data ED is inputted through the D latch 1-0, the data held in each of the D latches 1-0 through 1-31 is shifted to the D latch on the right successively (for example, the data of the D latch 1-0 is inputted to the D latch 1-1 and the data of the D latch 1-1 is inputted to the D latch 1-2).
Each of the coincidence detecting circuits 2, 3-0 through 3-31 always checks bit-by-bit coincidence/uncoincidence of the 32-bit unique word UW and comparison word UW-0 through UW-31 with the 32-bit data held in the 32-bit shift register 1.
That is, XNOR gates 100 through 131 of each of the coincidence detecting circuits 2, 3-0 through 3-31 compare the 32-bit unique word UW and comparison words UW-0 through 31 with the 32-bit data held in the 32-bit shift register 1 bit by bit. For example, the XNOR gate 100 of each of the coincidence detecting circuits 2, 3-0 through 3-31 compares the data (0th bit) stored in the D latch 1-31 with the 0th bit of the unique word UW and comparison words UW-0 through UW-31, respectively. In each of the coincidence detecting circuits 2, 3-0 through 3-31, only when all the XNOR gates 100 through 131 detect coincidence, the AND gate 132 outputs the coincidence detecting signal CD.
The reason why 33 pieces of coincidence detecting circuit 2, 3-0 through 3-31 are prepared is as follows. In case of digital communication based on the TDMA method, the above-mentioned "STD-28" standard of the RCR specifies that the data shall be made effective as if the original unique word is transmitted, not only when the transmitted unique word completely coincides with the original unique word UW but also even when an error is found in 1 bit only, in other words, when the 32-bit data held in the 32-bit shift register 1 coincides with any of the comparison words UW-0 through UW-31 stored in each one of the coincidence detecting circuits 3-0 through 3-31.
The OR gate 6 judges that the unique word is detected when the coincidence detecting signal CD is outputted from any of the coincidence detecting circuits 2, 3-0 through 3-31 and outputs the detecting signal indicating that the unique word has been detected. The detecting signal outputted from the OR gate 6 is inputted to the D latch 7 and latched at the falling edge of the next clock at and after that time point and outputted to the outside.
As described above, a conventional unique word detecting apparatus is designed to output the detecting signal indicating that the unique word has been detected in the case where when the error is only 1 bit even when the transmitted unique word does not completely coincide with the original unique word UW. For this reason, 33 pieces of coincidence detecting circuit with 32 pieces XNOR gates, respectively, are required, and the total of the XNOR gates which these coincidence detecting circuits 2, 3-0 through 3-31 possess exceeds 1000 pieces. In such an extremely large circuit scale, upsizing of the apparatus and increase in power consumption are certain to result, generating a fear of running counter to the original spirit of developing handy cordless telephones.
Because the conventional unique word detecting apparatus is not provided with means for recognizing the timing of the unique word transmission, it is necessary to judge whether the unique word is transmitted or not, every time the external data is inputted one bit to the 32-bit shift register 1. Consequently, when such judgment is made by a computer, etc., loads to the computer become so great that there is a fear for affecting other processing.
In addition, when the unique word to be transmitted is changed or the apparatus is applied to other standard, it is impossible to detect the changed unique word or that with a different standard unless the configuration is changed.